DC input on op amp integratorOp Amp Integrator not working with DC SourceOp-amp integrator response to square...
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DC input on op amp integrator
Op Amp Integrator not working with DC SourceOp-amp integrator response to square waveDesigning an integrator using an op ampAn integrator designCalculating Average voltage with integratorNon inverting integrator with referenceIntegrator as DC servoLF356 integrator simulation using LTspiceOp Amp integrator - limiting +Vsat to zero (ground)How does an op amp integrator work?
$begingroup$
I am trying to integrate a DC tension with a classic op amp integrator. The problem is : when I simulate my circuit on LT Spice, the output will always be equal to the VEE tension of the op amp regardless of the 1/RC coefficient. If anybody can help me on this problem, I put the circuit and the graphics below.
operational-amplifier amplifier dc integrator
asked 3 hours ago
Nicolas RoriveNicolas Rorive
161
New contributor
Nicolas Rorive is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
add a comment |
$begingroup$
I am trying to integrate a DC tension with a classic op amp integrator. The problem is : when I simulate my circuit on LT Spice, the output will always be equal to the VEE tension of the op amp regardless of the 1/RC coefficient. If anybody can help me on this problem, I put the circuit and the graphics below.
operational-amplifier amplifier dc integrator
asked 3 hours ago
Nicolas RoriveNicolas Rorive
161
New contributor
Nicolas Rorive is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
1
$begingroup$
You have a DC gain of 1000, and 2V applied to the input. Why wouldn't you expect the output to settle at the negative rail?
$endgroup$
– Phil G
3 hours ago
1
$begingroup$
Integration time is 1V/s and decay time is 1000s neglecting leakage current in cap and input bias offset. If steady state says the output is saturated, then look at the startup and initial condition. Null offsets are sometimes used in Integrators with low input Vio. You do not want to apply an offset, do you? if so why?
$endgroup$
– Sunnyskyguy EE75
3 hours ago
add a comment |
$begingroup$
I am trying to integrate a DC tension with a classic op amp integrator. The problem is : when I simulate my circuit on LT Spice, the output will always be equal to the VEE tension of the op amp regardless of the 1/RC coefficient. If anybody can help me on this problem, I put the circuit and the graphics below.
operational-amplifier amplifier dc integrator
asked 3 hours ago
Nicolas RoriveNicolas Rorive
161
New contributor
Nicolas Rorive is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
I am trying to integrate a DC tension with a classic op amp integrator. The problem is : when I simulate my circuit on LT Spice, the output will always be equal to the VEE tension of the op amp regardless of the 1/RC coefficient. If anybody can help me on this problem, I put the circuit and the graphics below.
operational-amplifier amplifier dc integrator
operational-amplifier amplifier dc integrator
asked 3 hours ago
Nicolas RoriveNicolas Rorive
161
New contributor
Nicolas Rorive is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 3 hours ago
Nicolas RoriveNicolas Rorive
161
New contributor
Nicolas Rorive is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 3 hours ago
Nicolas RoriveNicolas Rorive
161
New contributor
Nicolas Rorive is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 3 hours ago
Nicolas RoriveNicolas Rorive
161
asked 3 hours ago
Nicolas RoriveNicolas Rorive
161
161
New contributor
Nicolas Rorive is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
New contributor
Nicolas Rorive is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
Nicolas Rorive is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
1
$begingroup$
You have a DC gain of 1000, and 2V applied to the input. Why wouldn't you expect the output to settle at the negative rail?
$endgroup$
– Phil G
3 hours ago
1
$begingroup$
Integration time is 1V/s and decay time is 1000s neglecting leakage current in cap and input bias offset. If steady state says the output is saturated, then look at the startup and initial condition. Null offsets are sometimes used in Integrators with low input Vio. You do not want to apply an offset, do you? if so why?
$endgroup$
– Sunnyskyguy EE75
3 hours ago
add a comment |
1
$begingroup$
You have a DC gain of 1000, and 2V applied to the input. Why wouldn't you expect the output to settle at the negative rail?
$endgroup$
– Phil G
3 hours ago
1
$begingroup$
Integration time is 1V/s and decay time is 1000s neglecting leakage current in cap and input bias offset. If steady state says the output is saturated, then look at the startup and initial condition. Null offsets are sometimes used in Integrators with low input Vio. You do not want to apply an offset, do you? if so why?
$endgroup$
– Sunnyskyguy EE75
3 hours ago
1
1
$begingroup$
You have a DC gain of 1000, and 2V applied to the input. Why wouldn't you expect the output to settle at the negative rail?
$endgroup$
– Phil G
3 hours ago
$begingroup$
You have a DC gain of 1000, and 2V applied to the input. Why wouldn't you expect the output to settle at the negative rail?
$endgroup$
– Phil G
3 hours ago
1
1
$begingroup$
Integration time is 1V/s and decay time is 1000s neglecting leakage current in cap and input bias offset. If steady state says the output is saturated, then look at the startup and initial condition. Null offsets are sometimes used in Integrators with low input Vio. You do not want to apply an offset, do you? if so why?
$endgroup$
– Sunnyskyguy EE75
3 hours ago
$begingroup$
Integration time is 1V/s and decay time is 1000s neglecting leakage current in cap and input bias offset. If steady state says the output is saturated, then look at the startup and initial condition. Null offsets are sometimes used in Integrators with low input Vio. You do not want to apply an offset, do you? if so why?
$endgroup$
– Sunnyskyguy EE75
3 hours ago
add a comment |
2 Answers
2
active
oldest
votes
$begingroup$
The problem is with the solver, it's finding the wrong DC operating point. The solver first tries to find the point that the circuit is operating at, then runs the simulation. In the case of this integrator, it's wrong. So you either need to set initial conditions on the capacitor OR force the solver to recognize that the voltage is zero. One way to do this is with a PWL supply, starting it at zero, then at 1us or shortly after the simulation starts, then move the supply to 2V.
answered 3 hours ago
laptop2dlaptop2d
26k123381
$endgroup$
add a comment |
$begingroup$
You have a two volt signal applied to the input so it will always start saturated at the negative rail unless you set the capacitor initial conditions to something like 0V, or at least within the operating range of the op-amp.
You can try Ctrl-Right Click on the capacitor. Change as below to add IC=0 for zero volts at t=0, or select "skip initial operating point solution" in the simulation (which may have other side effects).
answered 3 hours ago
Spehro PefhanySpehro Pefhany
209k5160422
$endgroup$
add a comment |
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2 Answers
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$begingroup$
The problem is with the solver, it's finding the wrong DC operating point. The solver first tries to find the point that the circuit is operating at, then runs the simulation. In the case of this integrator, it's wrong. So you either need to set initial conditions on the capacitor OR force the solver to recognize that the voltage is zero. One way to do this is with a PWL supply, starting it at zero, then at 1us or shortly after the simulation starts, then move the supply to 2V.
answered 3 hours ago
laptop2dlaptop2d
26k123381
$endgroup$
add a comment |
$begingroup$
The problem is with the solver, it's finding the wrong DC operating point. The solver first tries to find the point that the circuit is operating at, then runs the simulation. In the case of this integrator, it's wrong. So you either need to set initial conditions on the capacitor OR force the solver to recognize that the voltage is zero. One way to do this is with a PWL supply, starting it at zero, then at 1us or shortly after the simulation starts, then move the supply to 2V.
answered 3 hours ago
laptop2dlaptop2d
26k123381
$endgroup$
add a comment |
$begingroup$
The problem is with the solver, it's finding the wrong DC operating point. The solver first tries to find the point that the circuit is operating at, then runs the simulation. In the case of this integrator, it's wrong. So you either need to set initial conditions on the capacitor OR force the solver to recognize that the voltage is zero. One way to do this is with a PWL supply, starting it at zero, then at 1us or shortly after the simulation starts, then move the supply to 2V.
answered 3 hours ago
laptop2dlaptop2d
26k123381
$endgroup$
The problem is with the solver, it's finding the wrong DC operating point. The solver first tries to find the point that the circuit is operating at, then runs the simulation. In the case of this integrator, it's wrong. So you either need to set initial conditions on the capacitor OR force the solver to recognize that the voltage is zero. One way to do this is with a PWL supply, starting it at zero, then at 1us or shortly after the simulation starts, then move the supply to 2V.
answered 3 hours ago
laptop2dlaptop2d
26k123381
answered 3 hours ago
laptop2dlaptop2d
26k123381
answered 3 hours ago
laptop2dlaptop2d
26k123381
answered 3 hours ago
laptop2dlaptop2d
26k123381
26k123381
add a comment |
add a comment |
$begingroup$
You have a two volt signal applied to the input so it will always start saturated at the negative rail unless you set the capacitor initial conditions to something like 0V, or at least within the operating range of the op-amp.
You can try Ctrl-Right Click on the capacitor. Change as below to add IC=0 for zero volts at t=0, or select "skip initial operating point solution" in the simulation (which may have other side effects).
answered 3 hours ago
Spehro PefhanySpehro Pefhany
209k5160422
$endgroup$
add a comment |
$begingroup$
You have a two volt signal applied to the input so it will always start saturated at the negative rail unless you set the capacitor initial conditions to something like 0V, or at least within the operating range of the op-amp.
You can try Ctrl-Right Click on the capacitor. Change as below to add IC=0 for zero volts at t=0, or select "skip initial operating point solution" in the simulation (which may have other side effects).
answered 3 hours ago
Spehro PefhanySpehro Pefhany
209k5160422
$endgroup$
add a comment |
$begingroup$
You have a two volt signal applied to the input so it will always start saturated at the negative rail unless you set the capacitor initial conditions to something like 0V, or at least within the operating range of the op-amp.
You can try Ctrl-Right Click on the capacitor. Change as below to add IC=0 for zero volts at t=0, or select "skip initial operating point solution" in the simulation (which may have other side effects).
answered 3 hours ago
Spehro PefhanySpehro Pefhany
209k5160422
$endgroup$
You have a two volt signal applied to the input so it will always start saturated at the negative rail unless you set the capacitor initial conditions to something like 0V, or at least within the operating range of the op-amp.
You can try Ctrl-Right Click on the capacitor. Change as below to add IC=0 for zero volts at t=0, or select "skip initial operating point solution" in the simulation (which may have other side effects).
answered 3 hours ago
Spehro PefhanySpehro Pefhany
209k5160422
answered 3 hours ago
Spehro PefhanySpehro Pefhany
209k5160422
answered 3 hours ago
Spehro PefhanySpehro Pefhany
209k5160422
answered 3 hours ago
Spehro PefhanySpehro Pefhany
209k5160422
209k5160422
add a comment |
add a comment |
Nicolas Rorive is a new contributor. Be nice, and check out our Code of Conduct.
Nicolas Rorive is a new contributor. Be nice, and check out our Code of Conduct.
Nicolas Rorive is a new contributor. Be nice, and check out our Code of Conduct.
Nicolas Rorive is a new contributor. Be nice, and check out our Code of Conduct.
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1
$begingroup$
You have a DC gain of 1000, and 2V applied to the input. Why wouldn't you expect the output to settle at the negative rail?
$endgroup$
– Phil G
3 hours ago
1
$begingroup$
Integration time is 1V/s and decay time is 1000s neglecting leakage current in cap and input bias offset. If steady state says the output is saturated, then look at the startup and initial condition. Null offsets are sometimes used in Integrators with low input Vio. You do not want to apply an offset, do you? if so why?
$endgroup$
– Sunnyskyguy EE75
3 hours ago